1. Field of the Invention
The present invention is directed to a semiconductor device and a method for fabricating the same, and in particular to a device isolation structure including a wide trench isolation structure and a fabrication method therefor.
2. Description of the Background Art
FIGS. 1A to 1E depict a conventional device isolation method for a semiconductor device.
As illustrated in FIG. 1A, a first silicon insulation layer 2 and a polycrystalline silicon layer 3 are sequentially formed on a semiconductor substrate 1, wherein a device formation region (or active region) 1a and a field isolation region 1b are defined.
As shown in FIG. 1B, the first silicon insulation layer 2 and the polycrystalline silicon layer 3 are etched and patterned such that an upper portion of the semiconductor substrate 1 corresponding to the field isolation region 1b can be exposed. The patterned first silicon insulation layer 2 and polycrystalline silicon layer 3 are utilized as a mask to selectively etch the exposed semiconductor substrate 1, thereby forming a plurality of wide trenches 4.
As illustrated in FIG. 1C, the surfaces of the plurality of trenches 4 and the polycrystalline silicon layer 3 are thermally oxidized, a second silicon insulation layer (not shown) is formed on their upper portion, and then a third silicon insulation layer (filling layer) 5 is formed on the second silicon insulation layer by a chemical vapor deposition so as to fill each trench. At this time, a surface of the filling layer 5 corresponding to the plurality of trenches 4 is caved.
As shown in FIG. 1D, the filling layer 5 within the trenches 4 is partially removed by a chemical-mechanical polishing or an etchback until an upper portion of the polycrystalline silicon layer 3 is exposed.
As illustrated in FIG. 1E, the polycrystalline silicon layer 3 and the first silicon insulation layer 2 are sequentially removed so that only the filling layer 5 remains in the respective trenches 4.
The conventional device isolation method has disadvantages. For instance, when forming devices having wide trenches into which a filling layer is deposited to fill in the wide trenches, and the filling layer becomes caved forming a dish-like shape if the filling layer is etched to make the surface of the semiconductor substrate level. As such, subsequently formed layers must be used to fill the caved shape filling layer, causing problems, particularly when the materials of the subsequently formed layers result in increased parasitic capacitance.
The present invention is directed to system that substantially obviates one or more of the problems experienced due to the above and other limitations and disadvantages of the related art.
It is an object of the present invention to prevent wide trenches by forming a dummy active pattern at an initial stage in a field isolation region in which the trenches will be formed.
It is another object of the present invention to make a capacitance of a parasitic capacitor, which is formed between a dummy active line and an active line in a field isolation region, similar to a capacitance of a parasitic capacitor in a conventional field isolation region.
Other and further objects, features and advantages of the present invention will be set forth in the description that follows, and in part will become apparent from the detailed description, or may be learned by practice of the invention.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a device isolation structure, including: a semiconductor substrate wherein a field isolation region including a plurality of dummy active regions and an active region are defined; a plurality of trenches formed among the regions; a filling layer filled in the trenches; a gate insulation layer formed on the semiconductor substrate having the filling layer; and a second conduction layer formed on the gate insulation layer.
In addition, in order to achieve the above-described objects of the present invention, there is provided a device isolation method for a semiconductor device, including: sequentially forming a first insulation layer and a first conduction layer on a semiconductor substrate wherein a field isolation region having dummy active regions and an active region are defined; etching and patterning the first insulation layer and the first conduction layer so that an upper portion of the semiconductor substrate on which trenches will be formed can be exposed; forming a plurality of trenches by using the patterned first insulation layer and first conduction layer as a mask and by etching the exposed semiconductor substrate; forming a filling layer on the first conduction layer including the plurality of trenches in order to be filled in the trenches; etching the filling layer until an upper portion of the first conduction layer is exposed; removing the first insulation layer and the first conduction layer so that the filling layer can remain only in the plurality of trenches; forming a gate insulation layer on the semiconductor and the filling layer filled in the plurality of trenches; and forming a second conduction layer on the gate insulation layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Thus, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of example only. Various changes and modifications that are within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. In fact, other objects, features and characteristics of the present invention; methods, operation, and functions of the related elements of the structure; combinations of parts; and economies of manufacture will surely become apparent from the following detailed description of the preferred embodiments and accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in various figures.